In microprocessor-based systems, it is often desirable to expand or fan-out the clock signal beyond the number of outputs available from the integrated circuit that produces the clock signal. Two solutions are commonly used to achieve the clock signal expansion. In the first solution, a master oscillator is used to drive one or more slave oscillators. This solution suffers from process variations during manufacture of various slave oscillators that cause the delay through one oscillator to differ slightly from the delay through another oscillator. In the second solution, a phase-locked-loop is used to synchronize the phase from two clocks, on one circuit board, that are of the same frequency. Such a solution is disclosed in U.S. Pat. No. 5,101,117 in which a common clock signal is provided to first and second voltage controlled delay lines. The first delay line delays the clock signal a fixed interval before supplying it to a first device. The second delay line receives the clock signal and delays it an adjustable time interval before supplying the delayed signal to a second device. The duration of the adjustable time delay is controlled by a voltage control signal that is generated by a phase-locked-loop circuit comparing the phase of the outputs on the two devices. A disadvantage of this solution is that it is only applicable to synchronizing two clock signals of the same frequency.
An improved alignment method is desired that overcomes the variation in delay through clock generating circuits due to process variations and, in addition, is capable of aligning clock signals of differing frequencies.